The present invention relates to an information processing system with a virtual storage having an address translation unit and particularly to an information processing system having a storage control circuit implemented by adopting high density packaging techniques utilized, for example, for fabricating integrated circuits.
An information processing system utilizing a virtual storage includes an address translation unit for translating a virtual address into a rear address. In the adddress translation unit, an address translation table is utilized for address translation. The address translation table is generally placed in a main storage unit and is referred to each time address translation takes place; therefore, the overhead due to the address translation increases. As a result, the information processing performance is reduced. Considering this problem, translation pairs of virtual and real addresses obtained by previous address translation operations are stored in a high-speed storage unit other than the main storage unit to minimize the overhead. The high-speed storage unit for storing pairs of translation addresses is called a translation look-aside buffer (referred to as TLB hereinafter).
Upon receiving a virtual address for accessing the main sotrage unit from a central processing unit, a storage control circuit first refers to the TLB. If a real address corresponding to the received virtual address has already been registered to the TLB, the storage control circuit obtains the objective real address from the TLB and accesses the main storage unit by use of the real address. On the other hand, if it is found as a result of referring to the TLB that the real address has not been registered to the TLB, the storage control circuit obtains the rear address using the address translation table, then accesses the main storage unit and registers the obtained address to the TLB.
As described above, the storage control circuit transfers and receives various interface signals, for example, virtual addresses and read/write data for the central processing unit, real addresses and read/write data for the main storage unit, and virtual and real addresses for the TLB.
Consequently, the storage control circuit becomes complex. To solve this problem of the resultant complexity, respective interface signal lines are provided for respective interface signals.
In recent years, there is a trend that large-scale integrated circuits have been increasingly utilized in order to produce a compact, high-speed, highly reliable information processing system. Since the number of interface signal lines are limited in such an integrated circuit because of component packaging, a large-scale integration has been difficult for a storage control circuit requiring a considerable number of interface signals, so that reduction of the number of interface signal lines has long been a pressing need. For the prior art, see U.S. Pat. No. 3,761,881 and U.S. Pat. No. 3,693,165.